Method to reduce read error rate for semiconductor resistive memory

ABSTRACT

During Magnetic Random Access Memory (MRAM) write operation with opposite electrical current direction through the Magnetic tunnel junction (MTJ), two different resistance of the MTJ can be stored at the MRAM cell as logic data “1” (data_1) and logic data “0” (data_0). The data_1 and data_0 can be read out by sensing the difference in resistance of the MTJ. However, due to the process uniformity, the distribution of resistance value for data_1 (R1) and the distribution of resistance value for data_0 (R0) can be overlapped. Those cells with the distribution of resistance value located in the overlapped region will produce a read error. An additional read and/or write cycle is added to the normal read or write operation to reduce read error rate. Multiple electrical reference current for read operation is added in order to widen the process window and manufacturing margin.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the advantages of the invention will be readilyunderstood, a more particular description of the invention brieflydescribed above will be rendered by reference to specific embodimentsthat are illustrated in the appended drawings. Understanding that thesedrawings depict only typical embodiments of the invention and are nottherefore to be considered to be limiting of its scope, the inventionwill be described and explained with additional specificity and detailthrough the use of the accompanying drawings, in which:

FIG. 1 is a drawing illustrating one embodiment of a Magnetic RandomAccess Memory (MRAM) cell;

FIG. 2 is a drawing illustrating one embodiment of a magnetic tunneljunction (MTJ);

FIG. 3 is a drawing illustrating one embodiment of effective MTJresistance;

FIG. 4 is a drawing illustrating one embodiment of write electricalcurrent for MTJ;

FIG. 5 is a drawing illustrating one embodiment of determine theeffective MTJ resistance and effective MTJ electrical current;

FIG. 6 is a drawing illustrating one embodiment of sense amplifier (SA)determines the data output;

FIG. 7 is a drawing illustrating one embodiment of non-overlapped Imtjdistribution;

FIG. 8 is a drawing illustrating one embodiment of non-overlapped Rmtjdistribution;

FIG. 9 is a drawing illustrating one embodiment of overlapped Imtjdistribution;

FIG. 10 is a drawing illustrating one embodiment of overlapped Imtjdistribution with additional Iref;

FIG. 11 is a drawing illustrating one embodiment of additional regionsas a result of additional Iref;

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to the semiconductor memory device, withparticular to a semiconductor resistive memory device such as Magnetic(or Magnetoresistive) Random Access Memory (MRAM), Phase Change memory(PCM), Resistance memory (RRAM).etc

The nonvolatile MRAM with Spin Transfer Torque (STT) programming hasbecome a topic of great interest. This SST MRAM can be manufactured withthe Complementary Metal Oxide Semiconductor (COMS) technology for boththe embedded application as well as the stand alone memory device. MRAMcombines the desirable attributes of today's memory technologies such asthe volatile Static Random Access Memory (SRAM), Dynamic Random AccessMemory (DRAM), and the Non-volatile Flash Memory. Some of the keyattributes are fast access time, random address selection, low cost,high density, and non volatility. However, variations in processparameters can lead to a large number of cell failures, severelyaffecting the yield of memory array. This invention is to provide asolution to improve the memory array yield due to the variation ofprocess parameters.

MRAM Cell Structure

As in FIG. 1, the conventional MRAM cell contains a switch device (T1)and Magnetic tunnel junction (MTJ). There are three terminals, the wordline (W.L), the Bit line (B.L) and Source Line (Source). The switchdevice normally can be Metal Oxide Semiconductor (MOS) transistor(n-channel MOS (nMOS), p-channel MOS (pMOS), or both)

A fundamental MTJ contains three basic layers as FIG. 2. It consists oftwo ferromagnetic layers separated by a thin tunnel dielectric. Thelower layer is “fixed” implying that its magnetic orientation cannot bechanged during operation. Whereas the magnetic orientation of the upper“free” layer can be changed. By controlling the direction of the writeelectrical current through the MTJ, the MTJ resistance can be changed asshown in FIG. 3 and FIG. 4. The effective MTJ resistance of theanti-parallel state is R1, and the effective MTJ resistance of theparallel state is R0. Based on the Magnetoresistance Ratio (MR), R1 isthe product of R0 times the sum of 1 and MR (R1=R0(1+MR)).

MRAM Read Operation

The MRAM read operation is performed by sensing the different MTJeffective resistance (R1 or R0) to generate logic data “1” (data_(—)1)or logic data “0” (data_(—)0) respectively.

One common way to sense the MTJ effective resistance (Rmtj) is to sensethe electrical current flow through the MTJ by using a bias voltagebetween the bit line (Vb1) and the source line (Vsource), and then turnon the switch device (T1) as shown on FIG. 5.

The electrical current sense amplifier (SA) determines the output databy comparing the MTJ electrical current (Imtj) with a suitable referenceelectrical current (Iref) as shown FIG. 6. In most cases, the Iref ischosen as half of the sum of Imtj_r1 and Imtj_r0, (½(Imtj_r1+Imtj_r0)),in order to achieve the largest read sensing margin. The sense amplifierwill sense the electrical current difference between Imtj_r1 (orImtj_r0) and Iref to output the logic data “1” or “0” respectively. Anideal relationship between Iref, Imtj_r1, and Imtj_r0 would be thepossible range (distribution) of Imtj_r0 and Imtj_r1 are not overlapped(Non-Overlapped) as shown in FIG. 7. Since the MTJ electrical current isproportional to the MTJ resistance, FIG. 7 can be redrawn as FIG. 8 byreplacing Imtj with Rmtj. The MRAM read operation margin will be betterif there are large separation region between Imtj_r1 and Imtj_r0, or anarrow distribution region of Imtj_r1 and Imtj_r0.

MRAM Write Operation

The MRAM write operation is achieved by applying different bias voltagebetween the Free layer and the Fix layer. The effective MTJ resistancecan switch between R1 and R0 respectively by the opposite direction ofelectrical current through MTJ. In another words, input data_(—)1 (R1)and data_(—)0 (R0) can be written by applying the correspondingelectrical current direction as FIG. 4. However, the data will notchange if the same data is written again because the effective MTJresistance (R1, R0), will not change if the same current direction isapplied.

MRAM Yield and Reliability

It is general practice in the semiconductor memory industry to continueshrink the size, or scaling, of the process technology every few years.Although the overall performance and cost of semiconductor memory devicecan be improved by scaling, statistical parametric variation is becominga serious concern which may potentially cause failure of the MRAM corecell during read or write operation. The major sources of processvariation in MTJ includes but not limited to, variations in tunnelingoxide thickness and variation in MTJ cross-sectional area . . . etc.

These parameters affect the static as well as the dynamic behavior ofMTJ resulting in possible failure of memory cell, such as read failureand inability to write to the cell. The problem is further aggravated inscaled technology with the lithography challenges. As the key parametersof MTJ such as tunnel oxide thickness and cross section area continue toshrink in more advanced process, the variation of those key MTJparameters varies significantly even with the slight change of processwindow. Consequently, designing and manufacturing a high yield SST MRAMbecomes a extremely challenging task.

MRAM Read Operation Failure

One of the major obstacles of MRAM production is the relative highoccurrence of read operation failure. Read operation failure occurs whenthe Imtj distribution changes from non-overlapped shape as FIG. 7 to anoverlapped shape as FIG. 9. These overlapped Imtj distribution occursmore likely in advanced process, smaller geometry, or in high densitymemory device.

As shown in FIG. 7, Imtj_r1 represents the electrical current of amemory cell which will be written with logic data “1” (data_(—)1), andImtj_r0 represent the electrical current of a memory cell which will bewritten with logic data “0” (data_(—)0). Overlapped occurs when the leftregion of Imtj_r0 become less than Iref as shown in region A of FIG. 9;or when the right region of Imtj_r1 become more than Iref as in region Bof FIG. 9. In another words, there are two type of cells located inregion A of FIG. 9, one was written with logic data “1” and the otherwas written with logic data “0”. Since the electrical current throughMTJ (Imtj) of those two cells are less than Iref, the read operationoutput data of those two cells will be logic data “1” regardless of theoriginal data content. The same behavior also occurs in region B of FIG.9 where the two type of cells read operation output data will be logicdata “0” regardless of the original data content. This incorrect readoperation output due to the overlapped distribution region as shown atFIG. 9 are commonly known as read operation failure.

MRAM Read Operation Failure Solution

In the present invention, we propose to embed series combination of readand/or write cycles into the original read operation. In another words,we will embed one or more read and/or write cycles into the originalread operation.

Assume there are two memory cells with different address location, butboth cells located at the region A of FIG. 9. One cell (Cell_X) has beenwritten logic data “0”, while the other cell (Cell_Y) has been writtenlogic data “1”. In the normal non-overlapped case as shown in FIG. 7,the output of read operation from Cell_X shall be data “0” and the readoutput from Cell_Y shall data “1”. However, if these two cells arelocated in the overlapped region A as FIG. 9, then the Imtj of these twocells are less than Iref, and the read output of those two cells will belogic data “1” regardless of the original input written data. In anotherwords, read operation failure for Cell_X occurs when its Imtj is in theoverlapped region A, and vice versa for Cell_Y where read operationfailure occurs when its Imj is in the overlapped region B.

In this invention, we take advantage of the fact that the resistance ofMTJ will not change if same data is to be written again to the same cellafter its read operation. When necessary, we propose to add a writecycle (1st write) to the same cell after the read (1st read) cycle. Theinput data (Data_W_(—)1) for this 1st write cycle can be the same orcomplementary as the output data (Data_R_(—)1) of the 1st read cycle.

When necessary, we propose to add another read cycle (2nd read) afterthe 1st write cycle. We also propose to perform a logic operation byadding a data comparison cycle between the output data from the 1st readcycle (Data_R_(—)1) and the output data from the 2nd read cycle(Data_R_(—)2).

As mentioned before, the resistance of MTJ will not change if the samedata is written again. Using Table A as an example, Cell_X has read anincorrect read output data “1” in column 2, will not change its datacontent “0” after the 1st write cycle in column 3 due to the fact thatsame data as the original data in column 1 was written. Since the datacontent of Cell_X do not change, it also means the Imtj_r1 of thisCell_X will not change. Since the Imtj_r1 of Cell_X stays the same, thiscell still remains in the same region A as FIG. 9. By performing a 2ndread cycle as in column 4 and a comparing cycle with the written data incolumn 3, we can determine a read failure has occurred for Cell_X.However, Cell_Y at Table A will have a complete different behavior. Asdata “0” in column 3 is being written during the 1st write cycle, thedata content of Cell_Y will change from data “1” to data “0”, and sowill the corresponding Imtj. The Imtj of Cell_Y changes from the Imj_r1region to the Imtj_r0 region as shown in FIG. 9. In another word, theImtj of Cell_Y has moved from the overlapped region A in FIG. 9 to thenon-overlapped region C in FIG. 9. By performing a 2nd read cycle as incolumn 4. then a correct output data (Data_Final) in column 5 can begenerated. In this case, the correct output data (Data_Final) in column5 is the logic inversion of the data output of the 2nd read cycle(Dtat_R_(—)2) in column 4. Table B represents this invention'sapplication for Cell_X and Cell_Y when the data content is in region B.

When necessary, we propose to add another write cycle (2nd write) afterthe 2nd read cycle in order to restore the original data back to thecell if the complementary data is to be written in column 3. Table A andTable B provide the samples to show the sequence of present invention.It demonstrates the final read output data (Data_final) in column 5 isthe inversion of the data output of the 2nd read cycle (Data_R_(—)2) incolumn 4. More importantly, the final read output data in column 5 iscorrect compares to the original input data in column 1, and any readfailure will be corrected.

TABLE A Cell_X and Cell_Y in the Region A FIG. (9) Column # 3 4 2 Writedata in Output data Output data the following from the 5 1 from the 1stwrite cycle (1st 2nd read Final data Cell Original read cycle writecycle) cycle output name data Data_R_1 Data_W_1 Data_R_2 Data_FinalCell_X 0 1 0 1 0 Cell_Y 1 1 0 0 1

TABLE B Cell_X and Cell_Y in the Region B FIG. (9) Column 3 4 2 Writedata in Output data Output data the following from the 5 1 from the 1stwrite cycle (1st 2nd read Final data Cell Original read cycle writecycle) cycle output name data Data_R_1 Data_W_1 Data_R_2 Data_FinalCell_X 0 0 1 1 0 Cell_Y 1 0 1 0 1

Increase MRAM Manufacture Margin and Process Window

In order to widen the MRAM process window to gain the manufacturemargin, we could take advantage of the more finite differences of theMTJ resistance regions. In present invention, we propose to divide thesingle Imtj distribution regions into more finite and smaller regions.This can be achieved by defining additional electrical reference currentsource (Iref) during read operation with the sense amplifier as in FIG.6. In another words, we propose to define additional electricalreference current (Iref_(—)1, and Iref_(—)2) as in FIG. 10. As shown inFIG. 11, more finite distribution regions (region E and region F) cannow be defined as a result of the additional Iref_(—)1 and Iref_(—)2.Region E is the read data “1” region that is on the left side ofIref_(—)1; while region F is the read data “0” region that is on theright side of Iref_(—)2. All of the additional Iref (Iref_(—)1,Iref_(—)2, Iref_(—)3 . . . etc) can be applied to the read cycle (1stread, 2nd read, 3rd read . . . etc) in this invention. In addition, allof the Iref read cycles can be performed in parallel in order to reducethe read access time as in FIG. 12.

Reference throughout this specification to “one embodiment,” “anembodiment,” or similar language means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment of the present invention. Thus,appearances of the phrases “in one embodiment,” “in an embodiment,” andsimilar language throughout this specification may, but do notnecessarily, all refer to the same embodiment.

The present invention may be embodied in other specific forms withoutdeparting from its spirit or essential characteristics. The describedembodiments are to be considered in all respects only as illustrativeand not restrictive. The scope of the invention is, therefore, indicatedby the appended claims rather than by the foregoing description. Allchanges which come within the meaning and range of equivalency of theclaims are to be embraced within their scope.

REFERENCE

-   U.S. Pat. No. 8,130,535 Two mask MTJ integration for STT MRAM, Kang    et al. Feb. 28, 2012-   U.S. Pat. No. 8,102,703 Nozieres, et al. Magnetic element with a    fast spin transfer torque writing procedure, Jan. 24, 2012-   U.S. Pat. No. 8,077,501, Zhang, et al. Thin seeded Co/Ni multilayer    film with perpendicular anisotropy for spintronic device    applications, Nov. 22, 2011-   U.S. Pat. No. 8,004,880, Bertin, et al. Non-volatile shadow latch    using a nanotube switch, Jul. 26, 2011-   WO/2012/033884, PCT/US2011/050779, Kim, et al. 15.03.2012-   WO/2012/009589, PCT/US2011/044094, Rao, et al. 19.01.2012-   WO/2010/148248, PCT/US2010/039075, Jung, et al. 23.12.2010-   WO/2011/153159, PCT/US2011/038599, Rao, et al. 08.12.2011-   WO/2011/116116, PCT/US2011/028699, Kim, et al. 22.09.2011

What is claimed is:
 1. The semiconductor nonvolatile memory such as Flash, MRAM, FcRAM . . . etc where as a memory cell array including a plurality of memory array in a matrix. Embed one or more combination of read and/or write cycles into one single read or write operation.
 2. These read and/or write cycles as in claim 1 can be performed in embedded mode inside the memory device, or performed in external mode outside the memory device by an external controller such as tester, memory controller, or device . . . etc.
 3. The embedded mode as in claim 2 can perform functional operation as read, write or test mode . . . etc.
 4. The external mode as in claim 2 can perform the function in hardware, software, firmware, or combination of hardware, software, firmware . . . etc.
 5. During the series read and/or write cycle as in claim 1, the input data of the write cycle is related to the output data from the previous read cycle. The input data of the write cycle can be the same or complementary of the output data from the previous read cycle.
 6. During the series read and/or write cycle as in claim 1, the read cycle can be used to define the region of the Magnetic Tunnel Junction electrical current (Imtj) and resistance (Rmtj) distribution.
 7. During the series read and/or write cycle as in claim 1, the final output data of this read operation will be generated by certain logic operation on the output data from one or more of the read cycles.
 8. The certain logic operation as in claim 7 can be performed in hardware, software, firmware, or combination of hardware, software, firmware . . . etc.
 9. During the series read and/or write cycle as in claim 1, single or multiple reference electrical current can be defined.
 10. Based on the multiple reference electrical current definition as in claim 9, multiple regions of Imtj and Rmtj can be defined.
 11. Each of the Imtj and Rmtj regions as in claim 10 can be different for each of the memory cell.
 12. During the series read and/or write cycle as in claim 1, the read and/or the write cycle can be performed in parallel.
 13. During the parallel read cycle as in claim 12, the specific region of the multiple Imtj and Rmtj regions can be determined.
 14. Each finite electrical and resistance MTJ regions can have its own separate read and/or write method.
 15. Each of the separate read and/or write method as in claim 14 can be different. 